1. Technical Field
The present invention relates to semiconductor memory apparatuses, and more particularly, to semiconductor memory apparatus with redundancy circuits.
2. Related Art
When during the manufacturing of a semiconductor memory apparatus a failure occurs in at least one cell of the semiconductor memory apparatus (i.e., the cell cannot function as memory), the semiconductor memory apparatus may be sorted as a bad product. As a result of semiconductor memory apparatuses becoming increasingly integrated, the number of cells with defects arising during the manufacturing processes has increased. When an entire semiconductor memory apparatus is sorted as a bad product because of a failure of only a certain cell of the semiconductor memory apparatus, inefficiency results in terms of the manufacturing yield and the manufacturing cost. In order to use a semiconductor memory apparatus with one or more failed cells as a good product, extra cells for replacing the failed cells may be designed in advance. These extra cells are called redundancy cells. When making an input or an output to or from an address, it may be necessary to check whether the address is normal or failed and to determine whether an access is to be made to a basic cell or a replaced cell. Circuits for such checking and determination are called redundancy circuits. A process for converting the semiconductor memory apparatus with one or more failed cells into a good product is called a repair process.
In the case of a semiconductor memory apparatus, a redundancy circuit may be designed for each row of directional wiring lines and each column of directional wiring lines, and may include a fuse block for recording the address information of a failed cell. When an access is made to the failed cell, the replaced normal cell is accessed instead of the failed cell through the repair process by using the fuse block.
A fuse block of a redundancy circuit may include a plurality of fuse wiring lines. By conducting a fuse cutting process, in which a specified fuse among a plurality of fuses is cut using laser, the address information of a repaired cell may be recorded. In order to record the address information of the repaired cell, a plurality of fuses may be needed. In general, fuses may be provided for the respective bits of an address. For example, in order to record the repair information of an 11-bit address, at least 11 fuses may be needed.
In order to record one repaired address, one fuse block may be needed. Therefore, as the number of fuse blocks increases, an increased number of failed cells may be replaced, whereby an increased number of semiconductor memory apparatuses with failed cells may be converted into good products. Since an increased area is occupied as the number of fuse blocks increases, limitations exist in integrating an increased number of fuse blocks. Thus, the number of fuse blocks to be designed may be determined based on chip size and manufacturing yield.
In the existing fuse blocks, the information of one repaired address may be recorded in one fuse block. If the information of repaired addresses increases, the number of fuse blocks needed and the area occupied by the redundancy circuit also increase. This serves as a factor for impeding the miniaturization of semiconductor memory apparatuses.
FIG. 1 is a block diagram illustrating a conventional redundancy circuit used in semiconductor memory apparatuses. The redundancy circuit includes a comparison unit 100, a fuse enable unit 200, and a determination unit 300.
For example, the comparison unit 100 may record/store information of an 11-bit repaired address. The comparison unit 100 may be configured to receive an 11-bit comparison address RA<2:12> when an enable signal EN is inputted, compare the received 11-bit comparison address RA<2:12> with the information of the repaired address, and output an 11-bit comparison result signal HIT<2:12>.
The fuse enable unit 200 may be configured to output a fuse enable signal FSEN based on whether or not the information of the repaired address is recorded in the comparison unit 100, when the enable signal EN is inputted.
The determination unit 300 may be configured to receive the fuse enable signal FSEN and the 11-bit comparison result signal HIT<2:12>, and activate and output a repair determination signal HITB<0> when all of the fuse enable signal FSEN and the 11 bits of the comparison result signal HIT<2:12> are activated.
When the enable signal EN is inputted, the redundancy circuit may compare the comparison address RA<2:12> with the repaired address. The redundancy circuit may activate and output the repair determination signal HITB<0> when the comparison address RA<2:12> and the repaired address are the same. And the redundancy circuit may deactivate and output the repair determination signal HITB<0> when the comparison address RA<2:12> and the repaired address are different from each other. Therefore, whether the comparison address RA<2:12> corresponds to the repaired address may be determined based on the repair determination signal HITB<0>.
The redundancy circuit of FIG. 1 shows one fuse block in which one repaired address information may be recorded in the fuse block. For example, in the case where there are two repaired addresses which are similar to each other as in Table 1, two fuse blocks are needed. If the information of repaired addresses increases as described above, the number of needed fuse blocks needed also increases regardless of whether the addresses are similar or not. As a result, the fuse blocks may occupy an inefficiently increased area, which acts as a factor for impeding the miniaturization of semiconductor memory apparatuses.
TABLE 1Address<2><3><4><5><6><7><8><9><10><11><12>First Repaired01111111111AddressSecond Repaired11111111111Address